An interrupt is a control signal sent to the microprocessor to draw its attention.

It is a type of signal to processor in which processor,on receiving the interrupt request,stops its  current operation and starts executing the subroutine associated with the interrupt signal.

Interrupt signal is – active low (0) or active high (1) signal used to send to a device to say “stop doing what you’re doing and listen to me. I’ve got something for you”. 

In general term, interrupt is a kind of BUZZER to stop the continous progess or break the continuity.


1)   Internal Interrupt

2)   Software Interrupt

3)   External Interrupt


As clear to its name, internal interrupts are those which are occurred due to Some Problem in the Execution.It seems to be used mostly to refer to what are also known as exceptions: interrupts that occur in response to a processing error, such as referencing an invalid address in memory, division by zero, or similar error condition.

 Arithmetic error – Invalid Instruction
– Addressing error – Hardware malfunction
– Page fault – Debugging – See more at:

– Arithmetic error – Invalid Instruction
– Addressing error – Hardware malfunction
– Page fault – Debugging – See more at:


A software interrupt is a type of interrupt  generated by executing an instruction is called software interrupt. A software interrupt is invoked by software, unlike a hardware interrupt, and is considered one of the ways to communicate with the kernel or to invoke system calls, especially during error or exception handling.

Software interrupts are generally used to make system calls.


External interruptions are generated by peripheral devices, such as keyboards, printers, communication cards, etc.The External Interrupt occurs when any Input and Output Device request for any Operation and the CPU will Execute that instructions first.

These interruptions are not sent directly to the CPU but they are sent to an integrated circuit whose function is to exclusively handle this type of interruptions.

Maskable AND Non-Maskable Interrupt

 An interrupt that can be disabled by writing some instruction is known as Maskable Interrupt.

A non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore.


There are two types of interrupts used in 8085 Microprocessor:

  1. Hardware Interrupts
  2. Software Interrupts

A software interrupts is a particular instructions that can be inserted into the desired location in the program. There are eight Software interrupts in 8085 Microprocessor.

  1. RST0
  2. RST1
  3. RST2
  4. RST3
  5. RST4
  6. RST5
  7. RST6
  8. RST7

We can calculate the vector address of these interrupts using the formula given below:  

Vector Address = Interrupt Number * 8
for example:
   Interrupt     Vector Address(in hexadecimal)     
  1. RST0   ————–  0000 ——————————— 0*8=0                                           
  2. RST1   ————–  0008 ——————————— 1*8=8   
  3. RST2   ————–  0010 ——————————— 2*8=16   
  4. RST3   ————–  0018 ——————————— 3*8=24 
  5. RST4   ————–  0020 ——————————— 4*8=32 
  6. RST5   ————–  0028 ——————————— 5*8=40 
  7. RST6   ————–  0030 ——————————— 6*8=48 
  8. RST7   ————–  0038 ——————————— 7*8=56 

 Shortcut method to learn with trick:

step 1 : first interrupt will be same i.e RST0 =0000

step 2: Now Add 8 to result of first interrupt  i.e 0+8= 0008

step 3: Now add 2 to result of second interrupt i.e 8+2=0010 

step 4 :  again add 8 into result of previous interrupt and the  again add 2 into result of previous interrupt so on.

Hardware Interrupt

   Interrupt     Vector Address(in hexadecimal)      
  1. TRAP—————-0024
  2. RST7.5————–003C
  3. RST6.5————–0034
  4. RST5.5————–002C
  5. INTR

 TRAP > RST7.5 > RST6.5 > RST5.5 > INTR

 TRAP has highest priority and RST7.5 has second highest priority and so on.


It is non-maskable edge and level triggered interrupt. TRAP has the highest priority and vector interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged.

  • There are two ways to clear TRAP interrupt.

               1.By resetting microprocessor (External signal)

               2.By giving a high TRAP ACKNOWLEDGE (Internal signal)


It has the second highest priority. It is maskable and edge level triggered interrupt. 

It can also be reset or masked by reseting microprocessor. 

It can also be resetted by DI instruction.


RST6.5 and RST5.5

BOTH interrupts are level triggered and maskable interrupts.

When RST6.5 pin is at logic 1, INTE  flip-flop is set. RST 6.5 has third highest priority and RST 5.5 has fourth highest priority.

IIt is disabled by,

               1.DI, SIM instruction

               2.System or processor reset.

               3.After reorganization of interrupt.


It is level triggered and maskable interrupt.

It has lowest priority.

The following sequence of events occurs when INTR signal goes high:

  1. The 8085 checks the status of INTR signal during execution of each instruction.
  2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled.
  3. On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.