Architecture MCQ


An 8KB direct mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprises 1 Valid bit, 1 Modified bit, as many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store
meta-data (tags) for the cache?
(A) 4864 bits (B) 6144bits (C) 6656bits (D) 5376bits
EXPLANATION:

8 KB cache = 8× 2^10 = 2^13,

block size = 32 = 2^5, so w = 5.

So, size of cache in no. of lines or blocks =
2^13/2^5 = 2^8, so r = 8.

blocks are 32 − w = 32 − 5 = 27.

So tag field = 32 − 8 − 5 = 19 bits.

total cache
size 2^8 rows. Total bits in cache control memory are 19+1+1 = 21.

So in 2^8 locations of cache, total bits
are 2^8 × 21 = 5373 bits. So answer is D.

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